This invention relates to the bit lines of a semiconductor memory such as a dynamic random-access memory (DRAM) or static random-access memory (SRAM).
Large-scale semiconductor memories are often designed with a certain amount of redundancy, so that if a fault is detected when the memory is tested during manufacture, the faulty part can be replaced by a redundant part and the memory can still be used. One fault that tends to occur is a short circuit between a bit line and a word line. In this case the shorted bit line is replaced by a redundant bit line.
Since the faulty bit line remains shorted to the word line, however, if the bit line is precharged to a different potential from the word line in the standby state, as is commonly the case, current leaks through the short circuit, degrading the current dissipation characteristics of the memory. Not infrequently, the memory exceeds its standby current leakage tolerance and has to be discarded even though the faulty bit line has been replaced.
Proposed methods of solving this problem include holding both bit and word lines at the ground potential in the standby state, and increasing the resistance of the bit-line or word-line material. These proposed solutions are unsatisfactory because they reduce the memory access speed. Another unsatisfactory solution is to add circuit elements to disable the precharging of faulty bit lines; the drawback of this approach is that it requires extra circuit area.